The present invention relates generally to semiconductor memory designs, and, more particularly, to a memory word-line driver design.
The core of a semiconductor memory comprises at least one two-dimensional memory cell array, where information is stored. Traditionally, word lines select rows, which activate cells, and bit lines select columns, which access (i.e., read or write) the cells. When a word line and a bit line are activated, a particular memory cell connected to them is selected.
To activate a word line, its voltage is normally set to a high voltage, which is equal to a positive supply voltage in complimentary-metal-oxide-semiconductor (CMOS) circuitry. Setting a word line to a low voltage, which is a voltage complimentary to the positive supply voltage, de-activates the word line. While the low voltage is customarily set to ground, or 0 V, the value for the high voltage can be different for various semiconductor manufacturing technologies. For instance, in a deep-sub-micron technology, a high voltage can be 1.2 V or even lower, while in a sub-micron technology the high voltage can be 2.5 V. But for a given memory chip and a given technology, the high voltage is normally designed to a fixed value, and this is particularly true for CMOS memory circuitry.